Samsung Advanced Institute of Technology

The innovation in silicon (Si)-based complementary metal-oxide-semiconductor (CMOS) technology is facing fundamental challenges in keeping up with the scaling requirement for meeting the surging demands in the era of data explosion. The primary challenge arises from the dimensional scaling limit of Si, in that severe carrier scattering occurs below the Si thickness of ~5 nm, leading to a substantial degradation of transistor performance. This necessitates a paradigm shift from the scaling of Si-based CMOS to the employment of alternative materials for channels and three-dimensional (3D) integration schemes. Two-dimensional (2D) semiconductors provide a promising solution for achieving such scaling needs, because their atomically thin profiles allow 2D semiconductors to maintain their electrical characteristics even at sub-nanometer scales. Furthermore, multi-sheet field-effect transistors (FETs) based on the 3D heterogeneous integration of 2D semiconductors are deemed as a viable path for aggressive cell scaling and unprecedented gate control. However, there still remain challenges to overcome for maturing 2D semiconductors-based FETs. Therefore, we present a milestone for realizing revolutionary advancements in the semiconductor industry through material innovations using 2D semiconductors and structural innovations through multi-sheet FETs.