Samsung Advanced Institute of Technology

Two-dimensional (2D) semiconductors have attracted tremendous interest as an atomically thin channel for the continued transistor scaling. However, despite many proof-of-concept demonstrations, the full potential of 2D transistors remains elusive. To this end, the fundamental merits and technological limits of 2D transistors need a critical assessment, reality check and objective projection. Here we review the promises and the current status of 2D transistors, and highlight the widely used device parameters (e.g., carrier mobility, contact resistance) could be frequently misestimated or misinterpreted, and may not be the most reliable performance metrics for benchmarking 2D transistors. We suggest the saturation or on-state current density, especially in the short channel limit, could provide a more reliable measure for assessing the potential of diverse 2D semiconductors, and should be applied for cross-checking different studies, especially when milestone performance metrics are claimed. We next summarize the key technical challenges in optimizing the channel, contacts, dielectric and substrate interfaces and outline the potential pathways to push the limit of 2D transistors; and lastly conclude with a prospect on the critical technical targets, the key technological hurdles to enable the lab-to-fab transition, and the potential opportunities arising in these atomically thin semiconductors.