Samsung Advanced Institute of Technology

Despite remarkable progress in two-dimensional material field-effect transistors (2D-FETs) for next-generation semiconductor chips^1？4, reliable wafer-scale device integration from concept genesis to industrial maturity remains challenging owing to the weak interfacial adhesion energy (IAE) between 2D materials and substrates^4？6. In addition, the conventional photo-lithography process, including a photochemical reaction and chemical etching, are often too aggressive and can damage delicate 2D materials with only surface atoms⁷. Therefore, IAE improvement and an alternative lithography method to seamlessly combine 2D materials with other substrates are essential for not only reliable device integration but also their merits implantation^8？11. Here, we systematically evaluated the nature of the IAE of various interfaces such as MoS₂/metal, MoS₂/insulator and MoS₂/2D crystals in large-scale interaction. The MoS₂/SiO₂ interface having the weakest IAE of 0.2 J/m² was modified using various self-assembled monolayers (SAMs) end-terminated with CF₃-, CH₃-, -SH, or NH₂-, which effectively modulated the IAE from ~0 to ~1 J/m² depending on electron ability of SAM end-termination. Based on this finding, we propose a new adhesion-lithography method based on the adhesion energy difference (IAE of MoS₂/CF₃-SAM ~ 0 J/m² and IAE of MoS₂/SH-SAM ~ 0.5 J/m²) and physical etching for MoS₂ patterning. Consequently, we successfully realized 100％ device yield with excellent uniformity as well as wafer-to-wafer reproducibility (statistic from more than 10000 devices in total) in 6-inch MoS₂ FETs due to the stable IAE of MoS₂/substrate and chemical-free in our patterning method.