Samsung Advanced Institute of Technology

The potential of monolithic 3D integration technology is largely dependent on the enhancement of interconnect characteristics which can lead to thinner stacks, better heat dissipation, and reduced signal delays. Carbon materials such as graphene, characterized by their sp2 hybridized carbons, are promising candidates for future interconnects due to their exceptional electrical, thermal conductivity and resistance to electromigration. However, a significant challenge lies in achieving low contact resistance between extremely thin semiconductor channels and graphitic materials. To address this issue, we propose an innovative wafer-scale synthesis approach that enables low contact resistance between dry-transferred 2D semiconductors and as-grown nanocrystalline graphitic interconnects. A hybrid graphitic interconnect with metal doping was used to reduce the sheet resistance by 84% compared to that of metal film of the same thickness. Furthermore, the introduction of a buried graphitic contact resulted in a contact resistance that is 22 times lower than that of bulk metal contacts (>40 nm). Transistors with this optimal structure were used to successfully demonstrate a simple logic function. The thickness of the active layer was maintained within a sub-7nm range, encompassing both channels and contacts. The ultra-thin transistor and interconnect stack developed in this work, characterized by a readily etchable interlayer and low parasitic resistance, paves the way for heterogeneous integration of future 3D ICs.