Samsung Advanced Institute of Technology

A novel nanometer-scale multilayer gate insulator engineering approach is introduced for simultaneous enhancement of the on-current and the bias stability of amorphous InGaZnO thin-film transistors (a-IGZO TFTs). Super-cycle modifications of the gate insulator atomic layer deposition (ALD) is leveraged, incorporating alternating layers of Al2O3, TiO2, and SiO2 for gate oxide stack optimization. Each gate insulator material is strategically selected for complementary functionalities, with Al2O3 layer improving the interface between gate insulator and semiconductor, TiO2 increasing the overall dielectric constant, and SiO2 suppressing charge trapping by serving as high-energy barrier between Al2O3 and TiO2. The ordering of each layer, especially separation of SiO2 and TiO2 layer with Al2O3, is predicted to be crucial in suppressing charge trapping and defect state density and is verified with electrical performance？？？？ comparison of the fabricated metal-insulator-metal capacitors and thin-film transistors. The optimized multilayer gate insulator demonstrates reduced insulator leakage current, roughly 1.76 times increase in on-current compared to single Al2O3 gate insulator, and enhanced bias stability of 5 mV threshold voltage shift under positive bias stress (PBS). Beyond device-level improvements, the cycling endurance of the 6-transistor 1-capacitor (6T1C) synaptic circuit is assessed, demonstrating faster read operation and enhanced weight update cycling stability with the engineered gate insulator compared to conventional designs. This innovative optimization addresses the current-mobility trade-off in IGZO TFT fabrication, enabling improved performance for very-large-scale-integration circuits and neuromorphic applications.